1. Field of the Invention
The present invention relates to semiconductor integrated circuit fabrication methods and, more particularly, to methods for forming spacers.
2. Background Art
FIG. 1A is a cross sectional view illustrating a gate structure 12 with a spacer 10 for use in fabricating integrated circuit metal-oxide-semiconductor field effect transistors (MOSFETs). As is well known, a trend in the semiconductor industry is to reduce as much as possible the size of integrated circuit structures. In scaling down the device size, a typical conventional process will cause the spacer 10 around the gate structure 12 to have a substantially vertical profile as shown in FIG. 1A. As is well known in the art of semiconductor integrated circuit fabrication, the vertical profile of the spacer 10 can undesirably result in the formation of "stringers" when etching a subsequent polysilicon layer deposited over the spacer 10. These stringers can detrimentally short circuit adjacent polysilicon lines formed from this polysilicon layer.
For example, as shown in FIG. 1B, a polysilicon layer 14 is subsequently deposited on the gate structure 12 and spacer 10. The polysilicon layer is then anisotropically etched to polysilicon lines 14A and 14B across the spacer 10 and gate structure 12, as shown in FIG. 1C. Because of the substantially vertical profile of the spacer 10, this etching process must be performed for a relatively long period of time (i.e., overetching) so as to ensure elimination of stringers that can be left behind on the spacer 10. Of course, the substantially vertical profile of the gate structure can detrimentally affect the step coverage of the polysilicon layer. In this example, stringers 16 can short circuit the lines 14A and 14B. Although overetching eliminates the stringers, it also reduces the process throughput and also requires that the polysilicon layer 14 have a greater thickness to compensate for the portion of the layer removed during the overetching process.
One solution to this problem is disclosed in U.S. Pat. No. 4,981,810 (the '810 patent) titled "Process For Creating Field Effect Transistors Having Reduced-Slope, Staircase-Profile Sidewall Spacers". In this type of solution, a spacer with a staircase-profile is formed to reduce the slope of the spacer. This type of solution is relatively complex in that it requires the deposition of at least two oxide layers. Further, in this type of solution, these two oxide layers are made to have different etch rates. For example, the aforementioned '810 patent discloses that an additional densification step can be used to create these different etch rates. Of course, it is generally desirable to reduce the number of process steps in the fabrication of an integrated circuit structure. Thus, there is a need for a simple method for forming a tapered spacer with relatively few process steps.